The present invention relates to a testing technique of semiconductor integrated circuits, and such a technique which is useful for application to communication LSIs.
In tests of semiconductor integrated circuits, there are included a DC (direct current) characteristic test, an AC (alternating current) characteristic test, and a function test. In the DC characteristic test, voltages of external terminals of an LSI and currents flowing through external terminals are measured in a DC manner. In the AC characteristic test, there are included measurements of the propagation delay time between input and output terminals, transition time of output waveforms, setup time, hold time, minimum clock pulse width, and maximum operation frequency. The function test is a test for determining whether the LSI operates without exhibiting an abnormality in its function when prescribed operation conditions are given to the LSI. In this function test, it is determined whether the function of the LSI is good by comparing signals output from the LSI with expected values when a test pattern is input to the LSI. For conducting such a function test, there are needed a pattern generating circuit for generating a test pattern and a comparing circuit for comparing signals output from the LSI with expected values. Some LSIs incorporate a pattern generating circuit and a comparing circuit, whereas some LSIs do not incorporate a pattern generating circuit and a comparing circuit. In the case where a pattern generating circuit and a comparing circuit are not incorporated, a pattern generating circuit and a comparing circuit disposed outside the LSI are used.
Furthermore, as described in JP-A-2-19051 (laid open on Jan. 23, 1990), there is known a modem control apparatus having a self test function for checking whether the transmission and reception function is normally performed. This modem control apparatus includes switch means for forming a loopback path by connecting modem ends of a receiving system control section and a transmitting system control section to each other when power is turned on, a pattern generator for supplying pattern data for a loopback test to an input side of the receiving system control section in synchronism with operation of the switch means, and a checker for comparing the pattern data output from the pattern generator with a result looped back via the receiving system control section, the switch means and the transmitting system control section and conveying a result of the comparison to the control sections.
Especially in such an LSI as to conduct multiplexing processing of n channels as in an LSI for communication, it is necessary to demultiplex a signal output from the pattern generating circuit to n channels. In this case, therefore, the pattern signal actually generated in the test pattern generating circuit must have a frequency that is n times the frequency of the test pattern used in the test of the LSI. As the clock frequency of the LSI becomes higher, design of a pattern generating circuit corresponding thereto becomes difficult. In addition, in a judging circuit, which receives a response pattern, signal synchronization is needed in signal comparison. If the frequency of the operation clock becomes high, however, signal synchronization also becomes difficult.
In JP-A-2-19051, detailed configurations in respective blocks are not shown. However, it is necessary to supply a signal generated by the pattern generator to the receiving system control section and supply it to the checker as well, for the purpose of comparing it with an output signal of the transmission system control section.